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august 2009 ? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 FAN7318B ? lcd backlight inverter drive ic FAN7318B lcd backlight inverter drive ic features ? high-efficiency single-stage power conversion ? wide input voltage range: 6v to 30v ? backlight lamp ballast and soft dimming ? minimal external components required ? precision voltage reference trimmed to 2% ? half-bridge topology ? soft-start ? pwm control at fixed frequency ? analog dimming function ? burst dimming function ? programmable striking frequency ? open-lamp protection ? open-lamp regulation ? over-voltage protection ? short-lamp protection ? cmp-high protection ? thermal shutdown ? 20-pin soic applications ? lcd tv ? lcd monitor description the FAN7318B is a lcd backlight inverter drive ic that controls p-n half-bridge topology. the FAN7318B provides a low-cost solution and reduces external components by integrating proprietary wave rectifiers for open-lamp protection and regulation. the operating voltage range of the FAN7318B is wide, so an external regulator isn?t necessary to supply the voltage to the ic. the FAN7318B provides various protections, such as open-lamp regulation, over-voltage protection, open- lamp protection, short- lamp protection, cmp-high protection, to increase the system reliability. the FAN7318B provides burst dimming and analog dimming. the FAN7318B is available in a 20-soic package. ordering information part number operating temperature package eco status packing method FAN7318Bm rail FAN7318Bmx -25 to +85c 20-lead, small outline integrated circuit (soic) rohs tape & reel for fairchild?s definition of eco status, please visit: http://www.fairchildsemi.com/com pany/green/rohs_green.html . protected under u.s. patent no. 5,652,479.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 2 FAN7318B ? lcd backli g ht inverter drive ic block diagram adim negative analog dimming protection error amp. max. 2v min. 0.5v 5v, max. 3ma uvlo 5.5v voltage reference & internal bias ref vin ct cmp 2v control logic bct bdim - + outb outa gnd - + 0.3v - + 1.34v short-lamp protection over-voltage protection olp1 olp2 - + on @ striking olr3 olr4 olr1 olr2 olp3 olp4 output driver oscillator min. & max. detector /full wave recifier max. min. tsd 150 o c - + hys. 0.45v - + max. 2v min. 0.5v 52 a burst sink current on 3.5v high cmp protection disable @ striking high_cmp - + 150 s delay striking off olp striking/normal min. & max. detector /full or half wave rectifier olp max. olp min. 0.7v/0.5v - + 17 pulses counter and olr<1.4v - + error. amp. source current change 1.35v ena - + 200k 1.34v - + - + 2.2v open-lamp regulation gm amp. 3.2 a error. amp. source current change 0 a timer disable @ striking 52 a burst sink current on if ena>2.5v, olp & slp disable. if ena<2.1v, olp & slp enable. v ref 50a @ ovp,slp 2a @ olp.cmp high 3v/1v @ striking/normal figure 1. internal block diagram
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 3 FAN7318B ? lcd backli g ht inverter drive ic pin configuration 1 2 3 4 5 6 7 8 20 19 18 17 16 15 14 13 outb ref timer olr4 vin olr2 olr1 olp3 adim bdim ct cmp ena 9 10 12 11 bct outa olp2 olp1 gnd olr3 olp4 figure 2. package diagram
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 4 FAN7318B ? lcd backli g ht inverter drive ic pin definitions pin # name description 1 timer this pin is for protection delay time setting. 2 cmp error amplifier output. typically, a compensation capacitor is connected to this pin from the ground. 3 adim this pin is the input for negative analog dimming. 4 ct this pin is for programming the switching fr equency. typically, a capacitor is connected to this pin from ground and a resistor is c onnected to this pin from the ref pin. 5 ref this pin is 5v reference output. typically, resist ors are connected to this pin from the ct pin and the bct pin. 6 bct this pin is for programming the frequency of t he burst dimming. typically, a capacitor is connected to this pin from ground and a resistor is connected to this pin from the ref pin. 7 bdim this pin is the input for negative burst dimming. the voltage range of 0.5 to 2v at this pin controls the burst-mode duty cycle from 0% to 100%. 8 ena this pin turns the ic on / off. 9 gnd this pin is the ground. 10 outb this pin is nmos gate-drive output. 11 outa this pin is pmos gate-drive output. 12 vin this pin is the supply voltage of the ic. 13 olr4 this pin is for open-lamp regulation. its functions are the same as the olr1 pin. 14 olp4 this pin is for open-lamp protection and feedback c ontrol of lamp currents. its functions are the same as the olp1 pin. 15 olr3 this pin is for open-lamp regulation. its functions are the same as the olr1 pin. 16 olp3 this pin is for open-lamp protection and feedback c ontrol of lamp currents. its functions are the same as the olp1 pin. 17 olr2 this pin is for open-lamp regulation. its functions are the same as the olr1 pin. 18 olp2 this pin is for open-lamp protection and feedback c ontrol of lamp currents. its functions are the same as the olp1 pin. 19 olr1 this pin is for open-lamp regulation and short-la mp protection. it has the same functions as other olr pins and is connected to the full-wave rectifier internally. when the maximum of rectified olr inputs is between 1.34v and 2v, the e rror amplifier output current is limited to 3.0a. when the maximum of rectified olr inputs reaches 2v, the error amplifier output current is 0a and its output voltage maintain s constant. the maximum of rectified olr inputs is inputted to the negative of another error amplifier for feedback control of lamp voltage. when the maximum of rectified olr inputs is more than 2.2v, another error amplifier for olr is operating and lamp voltage is regulated. in normal mode, if the maximum of rectified olr inputs is higher than 1.34v or if the minimum of rectified olr inputs is lower than 0.3v for a predetermi ned time by the timer pin capacitor and an internal current source 50a; the ic shuts down to protect the system in over-voltage condition or short-lamp condition, respectively. 20 olp1 this pin is for open-lamp protection and feedback control of lamp currents. it has the same functions as other olp pins and is connected to the half-wave rectifier and the full-wave rectifier internally. in striking mode, if the mi nimum of rectified olp inputs is less than 0.7v for a time predetermined by the timer pin capac itor and an internal current source or; in normal mode, if the minimum of rectifi ed olp inputs is less than 0.5v for another predetermined time by the timer pin capacitor and another internal current source; the ic shuts down to protect the system in open-lamp condition. the maximum of rectified olp inputs is inputted to the negative of the error amplifier for feedback control of lamp current.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 5 FAN7318B ? lcd backli g ht inverter drive ic absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v in ic supply voltage 6 30 v t a operating temperature range -25 +85 c t j operating junction temperature +150 c t stg storage temperature range -65 +150 c ja thermal resistance junction-air (1,2) 90 c/w p d power dissipation 1.4 w notes: 1. thermal resistance test board; size: 76.2mm x 114.3 mm x 1.6mm (1s0p); jedec standard: jesd51-2, jesd51-3. 2. assume no ambient airflow. pin breakdown voltage pin # name value unit 1 timer 7 2 cmp 7 3 adim 7 4 ct 7 5 ref 7 6 bct 7 7 bdim 7 8 ena 7 9 gnd 10 outb 30 11 outa 30 12 vin 30 13 olr4 7 14 olp4 7 15 olr3 7 16 olp3 7 17 olr2 7 18 olp2 7 19 olr1 7 20 olp1 7 v
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 6 FAN7318B ? lcd backli g ht inverter drive ic electrical characteristics for typical values, t a =25c, v in =15v, and -25c t a 85c, unless otherwise specifi ed. specifications to -25c ~ 85c are guaranteed by design based on final characterization results. symbol parameter test conditions min. typ. max. unit under-voltage lockout section (uvlo) v th start threshold voltage increase v in 4.9 5.2 5.5 v v thhys start threshold voltage hysteresis decrease v in 0.20 0.45 0.60 v i st startup current v in =4.5v 10 70 100 a i op operating supply current v in =15v, not switching 0.5 2.0 3.5 ma on/off section v on on-state input voltage 1.4 5.0 v v off off-state input voltage 0.7 v i sb standby current ena=0v 50 120 190 a r ena pull-down resistor ena=2v 120 200 280 k ? reference section (recommend 1f x7r capacitor) v 5 5v regulation voltage 4.9 5.0 5.1 v v 5line 5v line regulation 6 v in 30v 4 50 mv v 5load 5v load regulation 10a i 5 3ma 4 50 mv oscillator section (main) t a =25c, ct=220pf, rt=100k ? 101.3 105.0 108.3 f osc oscillation frequency ct=220pf, rt=100k ? 101 105 109 khz t a =25c, ct=220pf, rt=100k ? 126.5 131.0 135.5 f str oscillator frequency in striking mode ct=20pf, rt=100k ? 126 131 136 khz i ctdcs striking 1.03 1.18 1.33 ma i ctdc ct discharge current normal 770 870 970 a i ctcs ct charge current striking -15 -12 -9 a v cth ct high voltage 2 v v ctl ct low voltage 0.45 v oscillator section (burst) t a =25c, bct=4.7nf, brt=1.4m ? 321 330 342 f oscb burst oscillation frequency bct=4.7nf, brt=1.4m ? 317 330 343 hz i bctdc bct discharge current 20 26 32 a v bcth bct high voltage 2 v v bctl bct low voltage 0.5 v continued on the following page?
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 7 FAN7318B ? lcd backli g ht inverter drive ic electrical characteristics (continued) for typical values, t a =25c, v in =15v, and -25c t a 85c, unless otherwise specifi ed. specifications to -25c ~ 85c are guaranteed by design based on final characterization results. symbol parameter test conditions min. typ. max. unit analog dimming section adim=0v, t a =25c 1.225 1.310 1.402 adim=0v 1.212 1.310 1.408 adim=0.5v 1.16 av rexx reference voltage adim=1.0v 0.99 v error amplifier section l sin output sink current olp=2.5v, adim=2.5v 63 76 94 a l sur1 output source current 1 olp=0v, adim=0v -65 -50 -35 a l sur2 output source current 2 cmp=3v -1.4 -1.0 -0.6 a i bsin burst cmp sink current bdim=5v, bct=0v 41 52 63 a i olpi olp input current olp=2v 0 a i olpo olp output current olp=-2v -30 -20 -10 a olp=0.3v 0.34 v v lpfx rectifiers output of olp olp=1.5v 1.55 v v olpr olp input voltage range (3) -4 4 v open-lamp regulation section i olr1 striking, olr=1.6v -3.4 -2.8 -2.3 a i olr2 error amplifier source current for open-lamp regulation olr sweep 0 a v olr1 open-lamp regulation voltage 1 olr sweep 1.24 1.34 1.44 v v olr2 open-lamp regulation voltage 2 striking, olr sweep 1.88 1.98 2.08 v v olr3 open-lamp regulation voltage 3 2.1 2.2 2.3 v g molr olr error amplifier trans-conductance 180 310 440 mho i ors olr error amplifier sink current normal, olr=2.5v 40 60 80 a i olri olr input current olr=2.5v 0 a i olro olr output current olr=-2.5v -35 -25 -15 a v olrr olr input voltage range (3) -4 4 v continued on the following page?
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 8 FAN7318B ? lcd backli g ht inverter drive ic electrical characteristics (continued) for typical values, t a =25c, v in =15v, and -25c t a 85c, unless otherwise specifi ed. specifications to -25c ~ 85c are guaranteed by design based on final characterization results. symbol parameter test conditions min. typ. max. unit protection section v olp0 open-lamp protection voltage 0 (3) striking 0.65 0.70 0.75 v v olp1 open-lamp protection voltage 1 sweep olp 0.42 0.49 0.56 v v cmpr cmp-high protection voltage sweep cmp 3.4 3.5 3.6 v v hfbp high-fb protection voltage (3) 3.4 3.5 3.6 v v slp short-lamp protection voltage sweep timer 0.22 0.30 0.38 v v tmr1 timer threshold voltage 1 striking, sweep timer 2.87 3.02 3.17 v v tmr2 timer threshold voltage 2 sweep timer 1.0 1.1 1.2 v i tmr1 timer current 1 olp=0v 1.7 2.1 2.5 a i tmr2 timer current 2 olr=1.8v 40 50 60 a tsd thermal shutdown (3) 150 c v ovp over-voltage protection voltage sweep olr 1.24 1.34 1.44 v dcr ena2.3v olp disable/enable change voltage 2.1 2.3 2.5 v output section v pdhv pmos gate high voltage (3) v in =15v v in v v pdlv pmos gate low voltage v in =15v v in -9.0 v in -7.5 v in -6.5 v v ndhv nmos gate high voltage v in =15v 7.5 8.5 10.0 v v ndlv nmos gate low voltage (3) v in =15v 0 v v puv pmos gate voltage with uvlo activated v in =4.5v v in -0.3 v v nuv nmos gate voltage with uvlo activated v in =4.5v 0.3 v i pdsur pmos gate drive source current (3) v in =15v -300 ma i pdsin pmos gate drive sink current (3) v in =15v 400 ma i ndsur nmos gate drive source current (3) v in =15v 300 ma i ndsin nmos gate drive sink current (3) v in =15v -400 ma maximum / minimum duty cycle dc min minimum duty cycle (3) f osc =100khz 0 % dc max maximum duty cycle (3) f osc =100khz 45 49 % note: 3. these parameters, although guaranteed, are not 100% tested in production.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 9 FAN7318B ? lcd backli g ht inverter drive ic typical performance characteristics figure 3. start threshold voltage vs. temperature figure 4. start threshold voltage hysteresis vs. temperature figure 5. startup curre nt vs. temperature figure 6. operating curre nt vs. temperature figure 7. standby current vs. temperature figure 8. 5v regulation voltage vs. temperature
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 10 FAN7318B ? lcd backli g ht inverter drive ic typical performance characteristics (continued) figure 9. oscillation fre quency vs. temperature figure 10. oscillation frequency in striking vs. temperature figure 11. ct high voltage vs. temperature figure 12. ct low voltage vs. temperature figure 13. burst dimming frequency vs. temperature figure 14. bct discharge current vs. temperature
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 11 FAN7318B ? lcd backli g ht inverter drive ic typical performance characteristics (continued) figure 15. bct high voltage vs. temperature figure 16. bct low voltage vs. temperature figure 17. analog dimming reference voltage 0 vs. temperature figure 18. analog dimming reference voltage 05 vs. temperature figure 19. error amplifier source current 1 vs. temperature figure 20. error amplifier source current 2 vs. temperature
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 12 FAN7318B ? lcd backli g ht inverter drive ic typical performance characteristics (continued) figure 21. error amplifier source current for olr vs. temperature figure 22. error amplifier sink current vs. temperature figure 23. burst cmp sink current vs. temperature figure 24. olr error amplifier sink current vs. temperature figure 25. open-lamp protection voltage 1 vs. temperature figure 26. high-cmp protection voltage vs. temperature
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 13 FAN7318B ? lcd backli g ht inverter drive ic typical performance characteristics (continued) figure 27. short-lamp protection voltage vs. temperature figure 28. open lamp regulation voltage 1 vs. temperature figure 29. open lamp regulation voltage 2 vs. temperature figure 30. open lamp regulation voltage 3 vs. temperature figure 31. timer threshold voltage 1 vs. temperature figure 32. timer threshold voltage 2 vs. temperature
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 14 FAN7318B ? lcd backli g ht inverter drive ic typical performance characteristics (continued) figure 33. timer current 1 vs. temperature figure 34. timer current 2 vs. temperature
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 15 FAN7318B ? lcd backli g ht inverter drive ic functional description uvlo the under-voltage lockout (uvlo) circuit guarantees stable operation of the ic control circuit by stopping and starting it as a function of the v in value. the uvlo circuit turns on the control circuit when v in exceeds 5.2v. when v in is lower than 4.75v, the ic startup current is less than 100a. ena applying voltage higher than 1.4v to the ena pin enables the ic. applying voltage lower than 0.7v to the ena pin disables the ic. in terms of the protections, applying voltage higher than 2.5v to the ena pin disables olp and slp. applying voltage lower than 2.1v to the ena pin enables the olp and the slp. main oscillator in normal mode, the external timing capacitor (ct) is charged by the current flowing from the reference voltage source, which is formed by the timing resistor (rt) and the timing capacitor (ct). the sawtooth waveform charges up to 2v. once ct voltage reaches 2v, the ct begins discharging down to 0.4v. next, the ct starts charging again and a new switching cycle begins, as shown in figure 35. the main frequency is programmed by adjusting the rt and ct value. the main frequency is calculated as: [] osc 1 fhz 3.9585 rt 13650 rt ct ln 2.61 rt 13650 = ?? ?? ?? ?? ?? ?? (1) figure 35. main oscillator circuit in striking mode, the external timing capacitor (ct) is charged by the current flowing from the reference voltage source and 12 a current source, which increases the frequency. if the product of rt and ct value is constant, the striking frequency depends on ct and is calculated as: () () [] str 12 2 12 12 2 12 -6 -3 12 1 fhz 13.65 3i 4.55i rt ii rt rt ct ln 13.65 4.55i 3i rt ii rt i 12 10a,i 1.128 10a = ?? +? ?? ?? ? ?? ?? ?? +? ?? ?? ?? ? ?? = = q (2) burst dimming oscillator the burst dimming timing capacitor (bct) is charged by the current flowing from the reference voltage source, which is formed by the burst dimming timing resistor (brt) and the burst dimming timing capacitor (bct). the sawtooth waveform charges up to 2v. once the bct voltage reaches 2v, the capacitor begins discharging down to 0.5v. next, the bct starts charging again and a new burst dimming cycle begins, as shown in figure 36. the burst dimming frequency is programmed by adjusting the bct and brt values. the burst dimming frequency is calculated as: [] hz 4500 brt 0.026 4500 brt 0.039 ln bct brt 1 f oscb ? ? ? ? ? ? ? ? ? ? ? ? = (3) to avoid visible flicker, the burst dimming frequency should be greater than 120hz. figure 36. burst dimming oscillator circuit analog dimming for analog dimming, the lamp intensity is controlled with the external dimming signal (v adim ) and resistors. figure 37 shows how to implement an analog dimming circuit. error amp. - + v ref olp max . adim negative analog dimming v adim cmp figure 37. analog implementation circuit
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 16 FAN7318B ? lcd backli g ht inverter drive ic in full brightness, the maximum rms value of the lamp current is calculated as: [] = max _max 1 22 rms ref s iv a r (4) the lamp intensity is inversely proportional to v adim . as v adim increases, the lamp intensity decreases and the rms value of the lamp current is calculated as: [] [] max _max 22 0.30 rms ref s ref ref adim iv a r vv v a = =? (5) figure 38 shows the lamp current waveform vs. v adim in an analog dimming mode. 2.0 adim v ref lamp current 0 1.5 0.5 1.0 0.51.01.52.02.5 0 0.51.01.52.02.5 -10ma 10ma -5ma -15ma 15ma 5ma figure 38. analog dimming waveforms burst dimming lamp intensity is controlled with the bdim signal over a wide range. FAN7318B provi des polarity selection. when bdim is inputted, dc voltage or pwm pulse signal and bct sets the sawtooth waveform or dc voltage, respectively. this structure can be implemented as negative dimming polarity. when bdim voltage is lower than bct voltage, the lamp current is turned on; 0v on bdim commands full brightness. the duty cycle of the pwm pulse determines the lamp brightness. the lamp intensity is inversely proportional to bdim voltage. as bdim voltage increases, the lamp intensity decreases. figure 39 shows the lamp current waveform vs. dim in negative burst dimming mode. figure 39. negative burst dimming waveform using dc voltage burst dimming can be implemented, not only with dc voltage, but also using pwm pulse as the bdim signal. figure 40 shows how to implement burst dimming using pwm pulse as bdim signal. figure 40. negative burst dimming implementation circuit using an external pulse figure 41 shows the lamp current waveform vs. an external pulse in negative burst dimming mode. figure 41. negative burst dimming waveform using an external pulse
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 17 FAN7318B ? lcd backli g ht inverter drive ic during striking mode, burst dimming operation is disabled to guarantee continuous striking time. figure 42 shows burst dimming disabled during striking mode. 2 3 4 5 6 7 8 9 10 11 12 x 10 -3 0 0.5 1 1.5 2 2.5 2 3 4 5 6 7 8 9 10 11 12 x 10 -3 0 0.5 1 1.5 2 2 3 4 5 6 7 8 9 10 11 12 x 10 -3 -0.015 -0.01 -0.005 0 0.005 0.01 figure 42. burst dimming during striking mode when bdim is setting over 2.2v dc and bct is inputted pwm pulse signal, positive dimming polarity can be implemented. figure 43 shows how to implement burst dimming using pwm pulse as the bdim signal. figure 43. positive burst dimming implementation circuit using an external pulse figure 44 shows the lamp current waveform vs. an external pulse in positive burst dimming mode. figure 44. positive burst dimming waveform using an external pulse soft-start a soft-start circuit ensures a gradual increase in the input and output power. FAN7318B has no soft-start pin, but provides soft-start function using the first bct waveform. the first bct waveform limits cmp voltage at initial operation, so lamp cu rrent increases gradually, as shown in figure 45 and figure 46 figure 45. soft-start in normal mode figure 46. soft-start in burst dimming mode output drives FAN7318B is designed to drive p-n half-bridge mosfets with symmetric duty cycle. FAN7318B can drive p-mosfet directly without a level-shift capacitor and a zener diode. a fixed dead time of 500ns is introduced between two outputs at maximum duty cycle, as shown in figure 47. cmp ct sync t outa outb dead time 500ns at max. duty figure 47. mosfets gate drive signal
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 18 FAN7318B ? lcd backli g ht inverter drive ic lamp current feedback circuit FAN7318B has four olp pins for lamp current feedback and protections. the inputs of four olp pins are connected to the internal half-wave and full-wave rectifier circuits. the half-wave rectified signals of four olp inputs are connected to the maximum detector circuit. the full-wave rectified signals of four olp inputs are connected to the minimum detector circuit. two inputs of the four olp pins should be inverse phase with the other two inputs. lamp voltage feedback circuit FAN7318B has four olr pins for lamp voltage feedback and protections. the inputs of four olr pins are connected to the internal full-wave rectifier circuit. the full-wave rectified signals of the four olr inputs are connected to the maximum detector circuit. furthermore, they are connected to the minimum detector circuit for protections. protections the FAN7318B provides the following latch-mode protections: open-lamp regulation (olr), open-lamp protection (olp), short-lamp protection (slp), cmp- high protection and thermal shutdown (tsd). the latch is reset when v in falls to the uvlo voltage or ena is pulled down to gnd. the protection delay time can be adjusted by a capacitor between the timer pin and gnd. figure 48. protection timing delay assume that the timer pin capacitor is 1f. the striking time is calculated as: 1 13 1.5 2 str strike sur cv fv ts ia ? == = (6) the ovp and slp delay time are calculated as: _ 2 11 20 50 nor ovp slp sur cv fv tms ia ? == = (7) the cmp high protection and olp delay time are calculated as: _ 1 11 500 2 nor olp cmph sur cv fv tms ia ? == = (8) open-lamp regulation when the maximum of the rectified olr input voltages ( max olr v ) is more than 2v, the ic enters regulation mode and controls cmp voltage. the ic limits the lamp voltage by decreasing cmp source current. if max olr v is between 1.34v and 2v, cmp source current decreases to 3.0a. then, if max olr v reaches 2v, cmp source current decreases to 0a, so the cmp voltage remains constant and the lamp voltage also remains constant, as shown in figure 49. figure 49. open-lamp regulation in striking mode finally, if max olr v is more than 2.2v, the error amplifier for olr is operating and cmp sink current increases, so cmp voltage decreases and the lamp voltage maintains the determined value, as shown in figure 50. olr 0 cmp i cmp 2.2v 2v 0 -2v -2.2v 0 2.2v olr 2v olr figure 50. 2.2v open-lamp regulation over-voltage protection in normal mode, while max olr v is higher than 1.34v, the timer pin capacitor is charged by an internal current source of 50a. once the timer reaches 1v, the ic enters shutdown, as shown in figure 51. this protection is disabled in striking mode to ignite lamps reliably.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 19 FAN7318B ? lcd backli g ht inverter drive ic figure 51. over-voltage protection in normal mode in burst dimming mode, while max olr v is higher than 1.34v, burst dimming is disabled, so that the timer pin capacitor is charged continuously by an internal current source of 50a. once the timer reaches 1v, the ic enters shutdown, as shown in figure 52. figure 52. over-voltage protection in burst dimming mode open-lamp protection if the minimum of the rectified olp voltages ( min olp v ) is less than 0.7v during initial oper ation, the ic operates in striking mode for a time predetermined by the timer pin capacitor and an internal current source, 2a, as shown in figure 53. figure 53. open-lamp protection in striking mode the ic starts operating in striking mode and remains in striking mode until 17 pulses of min olp v higher than 0.7v and olr < 1.34v occur. if more than 17 pulses and olr < 1.34v, the ic changes from striking mode into normal mode, as shown in figure 54. figure 54. mode change from striking to normal after ignition, if min olp v is less than 0.5v for a time predetermined by the timer pin capacitor and an internal current source, 2a in normal mode, the ic is shut down, as shown in figure 55 and figure 56. olp1 olp2 olp3 olp4 150 s delay olp min. & max. detector /full or half wave rectifier olp min. 0.5v - + figure 55. olp in normal mode (configuration)
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 20 FAN7318B ? lcd backli g ht inverter drive ic figure 56. olp in normal mode in burst dimming mode, if min olp v is less than 0.5v for another time predetermined by the timer pin capacitor and an internal current source, 2a; the ic is shut down, as shown in figure 57. the open-lamp protection delay in burst dimming mode is shorter than in full brightness because a short-lamp condition is detected at rising interval of lamp voltage in burst dimming, then another internal current source is turned on during the interval. figure 57. olp in burst dimming mode applying voltage lower than 2.1v to the ena pin enables olp. applying voltage higher than 2.5v to the ena pin disables olp and is called as dcr mode. regardless of dcr mode, olp is enabled in striking mode. figure 58. olp disable in dcr mode short-lamp protection if the minimum of the rectified olr voltages ( min olr v ) is less than 0.3v for a time predetermined by the timer pin capacitor and a internal current source of 50a in normal mode, the ic is shut down, as shown in figure 59. this protection is disabled in striking mode to ignite lamps reliably. figure 59. short-lamp protection in normal mode in burst dimming mode, if min olr v is less than 0.3v for a time predetermined by the timer pin capacitor and a internal current source of 50a turned on only burst dimming on time, the ic is shut down, as shown in figure 60. slp protection delay changes, depending on burst dimming on duty ratio.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 21 FAN7318B ? lcd backli g ht inverter drive ic figure 60. slp in burst dimming mode applying voltage higher than 2.5v to the ena pin disables slp. applying voltage lower than 2.1v to the ena pin enables slp. figure 61. short-lamp protection disable in dcr mode cmp-high protection if cmp is more than 3.5v for a time predetermined by the timer pin capacitor and a internal current source of 50a in normal mode, the ic is shut down, as shown in figure 62. figure 62. cmp-high protection this protection is disabled by a pull-down resistor (a few m ) between cmp and gnd. if cmp voltage reaches 2.5v, cmp source current dec reases to 2a. determine a pull-down resistor value such that the whole of this current can flow through the resistor. if so, cmp-high protection can be disabled, as shown figure 63. this protection is disabled in striking mode to ignite the lamps reliably. figure 63. cmp-high protection disable by a pull- down resistor thermal shutdown the ic provides the function to detect abnormal over- temperature. if the ic temperature exceeds approximately 150 c, the thermal shutdown triggers.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 22 FAN7318B ? lcd backli g ht inverter drive ic typical application circuit (lcd backlight inverter) application device input voltage range number of lamps 22-inch lcd monitor FAN7318B 15v 10% 4 1. features ? high-efficiency, single-stage power conversion ? p-n half-bridge topology ? reduces required external components ? enhanced system reliability through protection functions 1timer cmp adim ct olr2 olp1 olr1 olp2 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ref bct bdim ena gnd outb olp3 olp3 olp4 olr4 vin outa bdim ic1 figure 64. typical application circuit
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 23 FAN7318B ? lcd backli g ht inverter drive ic physical dimensions 0.10 c c a see detail a notes: unless otherwise specified a) this package conforms to jedec ms-013, variation ac, issue e b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. e) landpattern standard: soic127p1030x265-20l pin one indicator 0.25 1 10 b ca m 20 11 b x 45 8 0 seating plane gage plane detail a scale: 2:1 seating plane land pattern recommendation f) drawing filename: mkt-m20brev3 0.65 1.27 2.25 9.50 13.00 12.60 11.43 7.60 7.40 10.65 10.00 0.51 0.35 1.27 2.65 max 0.30 0.10 0.33 0.20 0.75 0.25 (r0.10) (r0.10) 1.27 0.40 (1.40) 0.25 d) conforms to asme y14.5m-1994 figure 65. 20-lead, small outline integrated circuit (soic) package package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FAN7318B ? 1.0.0 24 FAN7318B ? lcd backli g ht inverter drive ic

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